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SPT7910
12-BIT, 10 MSPS, ECL, A/D CONVERTER
FEATURES
* * * * * * * * Monolithic 12-Bit 10 MSPS Converter 67 dB SNR @ 500 kHz Input On-Chip Track/Hold Bipolar 2.0 V Analog Input Low Power (1.4 W Typical) 5 pF Input Capacitance ECL Outputs
APPLICATIONS
* * * * * * * * Radar Receivers Professional Video Instrumentation Medical Imaging Electronic Warfare Digital Communications Digital Spectrum Analyzers Electro-Optics
GENERAL DESCRIPTION
The SPT7910 analog-to-digital converter is industry's first 12-bit monolithic analog-to-digital converter capable of sample rates greater than 10 MSPS. On board input buffer and track/ hold function assures excellent dynamic performance without the need for external components. Drive requirement problems are minimized with an input capacitance of only 5 pF. Inputs and outputs are ECL to provide a higher level of noise immunity in high speed system applications. An overrange output signal is provided to indicate overflow conditions. Output data format is straight binary. Power dissipation is very low at only 1.4 watts with power supply voltages of +5.0 and -5.2 volts. The SPT7910 also provides a wide input voltage range of 2.0 volts. The SPT7910 is available in a 32-lead ceramic sidebrazed DIP package and in die form. A commercial temperature range of 0 to +70 C is currently offered.
BLOCK DIAGRAM
VIN
INPUT BUFFER
4-BIT FLASH CONVERTER 4 ERROR CORRECTION, DECODING AND OUTPUT ECL DRIVERS
DIGITAL OUTPUT 12
ANALOG GAIN COMPRESSION PROCESSOR
TRACK AND HOLD AMPLIFIERS
ASYNCHRONOUS SAR
8
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA Phone: (719) 528-2300 FAX: (719) 528-2370
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 C
Supply Voltages VCC ............................................................... -0.3 to +6 V VEE ............................................................... +0.3 to -6 V Input Voltages Analog Input ............................................... VFBVINVFT VFT, VFB. ................................................... +3.0 V, -3.0 V Reference Ladder Current ..................................... 12 mA Output Digital Outputs .............................................. 0 to -30 mA Temperature Operating Temperature ................................... 0 to 70 C Junction Temperature ........................................... 175 C Lead Temperature, (soldering 10 seconds) .......... 300 C Storage Temperature ................................ -65 to +150 C
Note:
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, VCC =+5.0 V, VEE=-5.2 V, DVCC=+5.0 V, VIN=2.0 V, VSB=-2.0 V, VST=+2.0 V, fCLK=10 MHz, 50% clock duty cycle, unless otherwise specified. PARAMETERS Resolution DC Accuracy (+25 C) Integral Nonlinearity Differential Nonlinearity No Missing Codes Analog Input Input Voltage Range Input Bias Current Input Resistance Input Capacitance Input Bandwidth +FS Error -FS Error Reference Input Reference Ladder Resistance Reference Ladder Tempco Timing Characteristics Maximum Conversion Rate Overvoltage Recovery Time Pipeline Delay (Latency) Output Delay Aperture Delay Time Aperture Jitter Time Dynamic Performance Effective Number of Bits fIN=500 kHz fIN=1.0 MHz fIN=3.58 MHz TEST CONDITIONS TEST LEVEL MIN 12 SPT7910 TYP MAX UNITS Bits LSB LSB
Full Scale 250 kHz Sample Rate
V V VI VI VI VI V V V V VI V VI V IV V V V
2.0 0.8 Guaranteed 2.0 30 300 5 120 5.0 5.0 800 0.8
60
VIN=0 V 3 dB Small Signal
100
V A k pF MHz LSB LSB /C MHz ns
500
10 20 1 5 1 5
Clock Cycle
ns ns ps-RMS
10.2 10.0 9.5
Bits Bits Bits
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ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, VCC =+5.0 V, VEE=-5.2 V, DVCC=+5.0 V, VIN=2.0 V, VSB=-2.0 V, VST=+2.0 V, fCLK=10 MHz, 50% clock duty cycle, unless otherwise specified. PARAMETERS Dynamic Performance Signal-To-Noise Ratio (without Harmonics) fIN=500 kHz fIN=1 MHz fIN=3.58 MHz Harmonic Distortion1 fIN=500 kHz fIN=1.0 MHz fIN=3.58 MHz Signal-to-Noise and Distortion fIN=500 kHz fIN=1.0 MHz fIN=3.58 MHz Spurious Free Dynamic Range2 Differential Phase3 Differential Gain3 Digital Inputs Logic 1 Voltage Logic 0 Voltage Maximum Input Current Low Maximum Input Current High Pulse Width Low (CLK) Pulse Width High (CLK) Digital Outputs Logic 1 Voltage Logic 0 Voltage Power Supply Requirements Voltages VCC -VEE Currents ICC -IEE Power Dissipation Power Supply Rejection Ratio 50 to -2 V 50 to -2 V TEST CONDITIONS TEST LEVEL MIN SPT7910 TYP MAX UNITS
+25 C TMIN to TMAX +25 C TMIN to TMAX +25 C TMIN to TMAX +25 C TMIN to TMAX +25 C TMIN to TMAX +25 C TMIN to TMAX +25 C TMIN to TMAX +25 C TMIN to TMAX +25 C TMIN to TMAX +25 C +25 C +25 C
I IV I IV I IV I IV I IV I IV I IV I IV I IV V V V VI VI VI VI IV IV VI VI IV IV VI VI VI V
64 58 64 58 62 58 63 59 63 59 59 57 60 55 60 55 57 54
67 61 66 60 64 60 66 62 65 61 61 59 63 58 62 57 59 56 74 0.2 0.7
dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Degree % V V A A ns ns V V V V mA mA W LSB
-1.1 -500 -500 30 30 -1.1 200 300 -1.5 +750 +750 300 -0.8 -1.8
-1.5 +5.25 -5.45 190 160 1.8
+4.75 -4.95 150 125 1.4 1.0
Outputs Open (5 V0.25 V, -5.2 V 0.25 V)
Typical thermal impedances (unsoldered, in free air): 32L sidebrazed DIP. ja = 50 C/W. 164 distortion BINS from 4096 pt FFT. 2f IN = 1 MHz. 3f IN = 3.58 and 4.35 MHz.
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TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
TEST LEVEL I II III IV V VI
TEST PROCEDURE 100% production tested at the specified temperature. 100% production tested at TA=25 C, and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = 25 C. Parameter is guaranteed over specified temperature range.
Figure 1A: Timing Diagram
N N+1 N+2
t pwH
CLK
t pwL
CLK
td
N-2 N-1 DATA VALID N DATA VALID N+1
OUTPUT DATA
Figure 1B: Single Event Clock CLK
CLK
td
DATA VALID
OUTPUT DATA
Table I - Timing Parameters
PARAMETERS td tpwH tpwL DESCRIPTION CLK to Data Valid Prop Delay CLK High Pulse Width CLK Low Pulse Width MIN 30 30 TYP 5 300 MAX UNITS ns ns ns
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SPECIFICATION DEFINITIONS
APERTURE DELAY Aperture delay represents the point in time, relative to the rising edge of the CLOCK input, that the analog input is sampled. APERTURE JITTER The variations in aperture delay for successive samples. DIFFERENTIAL GAIN (DG) A signal consisting of a sine wave superimposed on various DC levels is applied to the input. Differential gain is the maximum variation in the sampled sine wave amplitudes at these DC levels. DIFFERENTIAL PHASE (DP) A signal consisting of a sine wave superimposed on various DC levels that is applied to the input. Differential phase is the maximum variation in the sampled sine wave phases at these DC levels. EFFECTIVE NUMBER OF BITS (ENOB) SINAD = 6.02N + 1.76, where N is equal to the effective number of bits.
DIFFERENTIAL NONLINEARITY (DNL) Error in the width of each code from its theoretical value. (Theoretical = VFS/2N) INTEGRAL NONLINEARITY (INL) Linearity error refers to the deviation of each individual code (normalized) from a straight line drawn from -Fs through +Fs. The deviation is measured from the edge of each particular code to the true straight line. OUTPUT DELAY Time between the clock's triggering edge and output data valid. OVERVOLTAGE RECOVERY TIME The time required for the ADC to recover to full accuracy after an analog input signal 125% of full scale is reduced to 50% of the full-scale value. SIGNAL-TO-NOISE RATIO (SNR) The ratio of the fundamental sinusoid power to the total noise power. Harmonics are excluded. SIGNAL-TO-NOISE AND DISTORTION (SINAD) The ratio of the fundamental sinusoid power to the total noise and distortion power. TOTAL HARMONIC DISTORTION (THD) The ratio of the total power of the first 64 harmonics to the power of the measured sinusoidal signal. SPURIOUS FREE DYNAMIC RANGE (SFDR) The ratio of the fundamental sinusoidal amplitude to the single largest harmonic or spurious signal.
N=
SINAD - 1.76 6.02
+/- FULL-SCALE ERROR (GAIN ERROR) Difference between measured full scale response [(+Fs) - (-Fs)] and the theoretical response (+4 V -2 LSBs) where the +FS (full scale) input voltage is defined as the output transition between 1-10 and 1-11 and the -FS input voltage is defined as the output transition between 0-00 and 0-01. INPUT BANDWIDTH Small signal (50 mV) bandwidth (3 dB) of analog input stage.
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TYPICAL PERFORMANCE CHARACTERISTICS
SNR vs Input Frequency
80 80
THD vs Input Frequency
70
70
fs = 10 MSPS
Total Harmonic Distortion (dB)
Signal-to-Noise Ratio (dB)
60
60
50
fs = 10 MSPS
50
40
40
30
30
20 10 -1 100 101
20 10-1 100 101
Input Frequency (MHz)
Input Frequency (MHz)
SNR, THD, SINAD vs Sample Rate
80
SINAD vs Input Frequency
80
SNR, THD
Signal-to-Noise and Distortion (dB)
70
70
SNR, THD, SINAD (dB)
60
60
SINAD
50
fs =10 MSPS
50
fin = 1 MHz
40
40
30
30
20 10 -1 100 101
20 10 -1 100 101
Sample Rate (MSPS)
Input Frequency (MHz)
Spectral Response
0
SNR, THD, SINAD vs Temperature
75
fS = 10 MSPS fIN = 1 MHz
SNR, THD, SINAD (dB)
-30
70
SNR
Amplitude (dB)
65
-60
THD
60
SINAD
-90
fs = 10 MSPS fin = 1 MHz
55
-120 0 1 2 Frequency (MHz) 3 4 5
50
-25
0
+25
+50
+75
Temperature (C)
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TYPICAL INTERFACE CIRCUIT
The SPT7910 requires few external components to achieve the stated operation and performance. Figure 2 shows the typical interface requirements when using the SPT7910 in normal circuit operation. The following section provides a description of the pin functions and outlines critical performance criteria to consider for achieving the optimal device performance. POWER SUPPLIES AND GROUNDING The SPT7910 requires the use of two supply voltages, VEE and VCC. Both supplies should be treated as analog supply sources. This means the VEE and VCC ground returns of the device should both be connected to the analog ground plane. All other -5.2 V requirements of the external digital logic circuit should be connected to the digital ground plane. Each power supply pin should be bypassed as closely as possible to the device with .01 F and 10 F capacitors as shown in figure 2. The two grounds available on the SPT7910 are AGND and DGND. DGND is used only for ECL outputs and is to be referenced to the output pulldown voltage. These grounds are not tied together internal to the device. The use of ground planes is recommended to achieve the best performance of Figure 2 - Typical Interface Circuit
CLK-IN CLK 2 CLK VIN1 VIN2
the SPT7910. The AGND and the DGND ground planes should be separated from each other and only connected together at the device through an inductance or ferrite bead. Doing this will minimize the ground noise pickup. VOLTAGE REFERENCE The SPT7910 requires the use of two voltage references: VFT and VFB. VFT is the force for the top of the voltage reference ladder (+2.5 V typ), VFB (-2.5 V typ) is the force for the bottom of the voltage reference ladder. Both voltages are applied across an internal reference ladder resistance of 800 ohms. In addition, there are five reference ladder taps (VST,VRT1, VRT2, VRT3, and VSB). VST is the sense for the top of the reference ladder (+2.0 V), VRT2 is the midpoint of the ladder (0.0 V typ) and VSB is the sense for the bottom of the reference ladder (-2.0 V). VRT1 and VRT3 are quarter point ladder taps (+1.0 and -1.0 V typical, respectively). The voltages seen at VST and VSB are the true full scale input voltages of the device when VFT and VFB are driven to the recommended voltages (+2.5 V and -2.5 V typical respectively). VST and VSB should be used to monitor the actual full scale input voltage of the device. VRT1, VRT2 and VRT3 should not be driven to the expected ideal values as is commonly done with standard flash converters. When not being used, a decoupling capacitor of .01 uF connected to AGND from each tap is recommended to minimize high frequency noise injection.
CLK-IN Analog Input Analog Input
D12 (OVERRANGE) Coarse A/D 4 D11 (MSB) D10 D9
10 F
.01 F
IC1
VOUT 2 VIN (REF-03) Trim GND 4
ANALOG PRESCALER VFT
D8
Decoding Network
6 R1 10 k
+ +2.5 V
D7
Digital Outputs
R VST .01 F R2* 30 k
5
T/H AMPLIFIER BANK
D6 D5 D4 D3 D2
2R SUCCESSIVE INTERPOLATION STAGE # i
+5 V .01 F 7 1 10 F +5 V R4 10 k
+
3 IC2
(OP-07) +
2 -5.2 V 4
.01 F
VRM .01 F
2R
2R R3* 30 k VSB SUCCESSIVE INTERPOLATION STAGE # N
D1 D0 (LSB) 13 x 50
8 6
2R
*R2 and R3 matched to 0.1%
.01 F -2.5 V 10 F + VFB
R
.01 F
VEE DG DG VCC VCC VEE AG AG
+ 10 F .01 F + -5.2 V D1 -5.2 V +5 V D2 +5 V AGND ( 5 V RTN & -5.2 V RTN ) 10 F .01 F
L 10 H + 10 F .01 F
DGND ( -2 V RTN )
-2 V
NOTE: D1=D2=1N5817 or equivalent. (Used to prevent damage caused by power sequencing.)
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The analog input range will scale proportionally with respect to the reference voltage if a different input range is required. The maximum scaling factor for device operation is 20% of the recommended reference voltages of VFT and VFB. However, because the device is laser trimmed to optimize performance with VSB and VST equal to -2.0 V and +2.0 V respectively, the accuracy of the device will degrade if operated beyond a 2% range. The following errors are defined: +FS error = top of ladder offset voltage = (+FS -VST) -FS error = bottom of ladder offset voltage = (-FS -VSB) Where the +FS (full scale) input voltage is defined as the input approximately 1 LSB above the output transition of 1--10 and 1--11 and the -FS input voltage is defined as the input approximately 1 LSB below the output transition of 0--00 and 0--01. An example of a reference driver circuit recommended is shown in figure 2. IC1 is REF-03, the +2.5 V reference with a tolerance of 0.6% or 0.015 V. The potentiometer R1 is 10 k and supports a minimum adjustable range of up to 150 mV. IC2 is recommended to be an OP-07 or equivalent device. R2 and R3 must be matched to within 0.1% with good TC tracking to maintain a 0.3 LSB matching between VFT and VFB. If 0.1% matching is not met, then potentiometer R4 can be used to adjust the VFB voltage to the desired level. R1 and R4 should be adjusted such that VST and VSB are exactly +2.0 V and -2.0 V respectively. ANALOG INPUT VIN1 and VIN2 are the analog inputs. Both inputs are tied to the same point internally. Either one may be used as an analog input sense and the other for an input force. The inputs can also be tied together and driven from the same source. The full scale input range will be 80% of the reference voltage or 2 volts with VFB=-2.5 V and VFT=+2.5 V. The drive requirements for the analog inputs are minimal when compared to conventional Flash converters due the SPT7910's extremely low input capacitance of only 5 pF and very high input impedance of 300 k. For example, for an input signal of 2 V p-p with an input frequency of 10 MHz, the peak output current required for the driving circuit is only 628 A.
CLOCK INPUT The clock inputs (CLK, CLK ) are designed to be driven differentially with ECL levels. Differential clock driving is highly recommended to minimize the effects of clock jitter. The clock may be driven single ended since CLK is internally biased to -1.3 V. CLK may be left open, but a .01 F bypass capacitor to AGND is recommended. As with all high speed circuits, proper terminations are required to avoid signal reflections and possible ringing that can cause the device to trigger at an unwanted time. The clock input duty cycle should be 50% where possible, but performance will not be degraded if kept within the range of 40-60%. However, in any case the clock pulse width (tpwH) must be kept at 300 ns maximum to ensure proper operation of the internal track and hold amplifier. (See the timing diagram.) The analog input signal is latched on the rising edge of the CLK. DIGITAL OUTPUTS The format of the output data (D0-D11) is straight binary. (See table II.) These outputs are ECL 10K and 10KH compatible with the output circuit shown in figure 3. The outputs are latched on the rising edge of CLK with a propagation delay of 5 ns. There is a one clock cycle latency between CLK and the valid output data (see timing diagram). These digital outputs can drive 50 ohms to ECL levels when pulled down to -2 V. Output loading pulled down to -5.2 V is not recommended. The total specified power dissipation of the device does not include the power used by these loads. The additional power used by these loads can vary between 10 and 300 mW typically (including the overrange load) depending on the output codes. If lower power levels are desired, the output loads can be reduced, but careful consideration to the resistive and capacitive loads in relation to the operating frequency must be considered. Table II - Output Data Information
ANALOG INPUT >+2.0 V + 1/2 LSB +2.0 V -1 LSB 0.0 V -2.0 V +1 LSB <-2.0 V OVERRANGE D12 1 O O O O OUTPUT CODE D11-DO 1111 1111 1111 1111 1111 111O
OOOO OOOO OOOO OOOO OOOO OOOO OOOO OOOO OOOO
(O indicates the flickering bit between logic 0 and 1).
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Figure 3 - Output Circuit
AGND DGND
EVALUATION BOARD
* *
*
Data Out
*
OVERRANGE OUTPUT The OVERRANGE OUTPUT (D12) is an indication that the analog input signal has exceeded the full scale input voltage by 1 LSB. When this condition occurs, the output will switch to logic 1. All other data outputs are unaffected by this operation. This feature makes it possible to include the SPT7910 into higher resolution systems.
The EB7910 Evaluation Board is available to aid designers in demonstrating the full performance of the SPT7910. This board includes a reference circuit, clock driver circuit, output data latches and an on-board reconstruction of the digital data. An application note (AN7910) describing the operation of this board as well as information on the testing of the SPT7910 is also available. Contact the factory for price and availability.
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PACKAGE OUTLINE
32-Lead Sidebrazed
32
H
I 1 G A E F C B D
INCHES MIN MAX 0.081 0.016 0.095 0.040 0.175 1.580 0.585 0.009 0.600 0.099 0.020 0.105 .050 typ 0.225 1.620 0.605 0.012 0.620 MILLIMETERS MIN MAX 2.06 0.41 2.41 1.02 4.45 40.13 14.86 0.23 15.24 2.51 0.51 2.67 1.27 5.72 41.15 15.37 0.30 15.75 15.75
J
SYMBOL A B C D E F G H I J
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PIN ASSIGNMENTS
DGND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 32 31 30 29 28 27 26
PIN FUNCTIONS
V
NAME DGND AGND D0-D11 D12 CLK CLK VEE VCC VRT1,VRT2,VRT3 VIN1, VIN2 VFT VST VFB VSB
FUNCTION Digital Ground Analog Ground ECL Outputs (D0=LSB) ECL Output Overrange Clock Inverted Clock -5.2 V Supply +5.0 V supply Voltage Reference Taps Inputs (tied together at the die) Force for Top of Reference Ladder Sense for Top of Reference Ladder Force for Bottom of Reference Ladder Sense for Bottom of Reference Ladder
EE
AGND V V V V V V V
CC FB SB RT1 RT2 IN1 IN2 RT3 ST FT CC
DIP
25 24 23 22 21 20 19 18 17
V V V V
AGND V
EE
DGND 15 CLK
16
CLK
ORDERING INFORMATION
PART NUMBER SPT7910SCJ SPT7910SCU TEMPERATURE RANGE 0 to +70 C +25 C PACKAGE 32L Sidebrazed DIP Die*
*Please see the die specification for guaranteed electrical performance.
Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby expressly granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited. WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably expected to result in significant personal injury or death. Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.
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